The present invention generally relates to semiconductor devices and, more particularly, to a semiconductor device having a large-area silicide layer and a process for fabricating such a device.
Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One such silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor.
The principal elements of a typical MOS semiconductor device are illustrated in FIG. 1. The device generally includes a semiconductor substrate 101 on which a gate electrode 103 is disposed. The gate electrode 103 acts as a conductor. An input signal is typically applied to the gate electrode 103 via a gate terminal (not shown). Heavily-doped source/drain regions 105 are formed in the semiconductor substrate 101 and are connected to source/drain terminals (not shown). The source/drain regions 105 may, for example, be lightly-doped drain (LDD) source/drain regions as shown. As illustrated in FIG. 1, the typical MOS transistor is symmetrical, which means that the source and drain are interchangeable. Whether a region acts as a source or drain depends on the respective applied voltages and the type of device being made (e.g., PMOS, NMOS, etc.). Thus, as used herein, the term source/drain region refers generally to an active region used for the formation of a source or drain.
A channel region 107 is formed in the semiconductor substrate 101 beneath the gate electrode 103 and separates the source/drain regions 105. The channel is typically lightly doped with a dopant of a type opposite to that of the source/drain regions 105. The gate electrode 103 is generally separated from the semiconductor substrate 101 by an insulating layer 109, typically an oxide layer such as SiO2. The insulating layer 109 is provided to prevent current from flowing between the gate electrode 103 and the source/drain regions 105 or channel region 107.
In a completed device structure, a silicidation layer 111 is typically formed over the source/drain regions 105 and the gate electrode 103. The silicidation layer 111 generally facilitates contact between the gate electrode 103 and source/drain regions 105 and subsequent metal lines. The silicidation layer 111 also serves to reduce the sheet resistance of the gate electrode 103 and source/drain regions 105.
The silicidation layer 111 is typically formed by forming spacers 113 on sidewalls of the gate electrode 203, depositing a layer of metal, such as tungsten or cobalt, over the substrate 101 and annealing the wafer. During the annealing process, the deposited metal reacts with underlying silicon and forms a metal silicidation layer. The silicidation layer 211 generally expands outward from the original surface of the underlying silicon. The spacers 113 play an important role in separating the silicidation layer 111 over the source/drain regions 105 from the silicidation layer 111 on the gate electrode 103. Without the spacers 113, conventionally formed silicidation layers would short the source/drain regions 105 and the gate electrode 103. A more detailed description of silicidation layers and the fabrication thereof may be found in S. Wolf, Silicon Processing for the VLSI Era, Vol. 2: Processing Integration, pp. 143-153 and 157-158.
The present invention generally relates to a semiconductor device having a large-area silicide layer. The silicide area generally has a surface area which is larger than silicide layers formed using conventional techniques. This, for example, reduces the resistance of the active regions of the semiconductor device and enhances device performance.
In accordance with one embodiment of the invention, a process for fabricating a semiconductor device is provided in which a gate insulating layer is formed over a silicon substrate. A gate electrode is formed over the gate insulating layer. A silicide layer is formed over an active region of the substrate adjacent the gate electrode and in contact with the gate insulating layer. The silicide layer may, for example, have a height which is less than the thickness of the gate insulating layer. The active region may, for example, be a source/drain region.
A semiconductor device, consistent with one embodiment of the invention, includes a silicon substrate, a gate insulating layer disposed over the silicon substrate, a gate electrode disposed over the gate insulating layer, and at least one active region disposed adjacent the gate electrode. Formed over the active region and in contact with the insulating layer is a silicide layer. The active region may, for example, be a source/drain region.